Nowadays I have trouble talking about asynchronous interfaces for SPDIF and AES because everyone else is only thinking in terms of USB interfaces.
USB interfaces are a whole other ball of wax I don't want to think about, along with I2S, as I have detailed in an earlier post, because they inhibit the chaining of digital devices and generally lock you in to proprietary software. That kills the fun, and right now I can't use those interfaces anyway because my style of digital audio relies upon the chaining of digital audio devices, such as the Behringer 2496 DEQ units I use as crossovers and room correction, and the Tact RCS 2.0 I use for volume, balance, and polarity adjustment (though it is capable of much more). USB and I2S assume you are connecting a computer to a DAC, with nothing in between. In principle you could chain USB and I2S devices....but you'd have to write all new operating systems for every step of the chain.
Anyway, SPDIF/AES interfaces can also be implemented in synchronous and asynchronous versions, the asynchronous version generally involving ASRC -- Asynchronous Sample Rate Conversion.
ASRC has always seemed very fishy to me, because it essentially relies upon endless interpolation. The data presented to the ultimate digital converter is not the data you started with.
No interpolation process can be perfect, and especially when in this case it involves guesswork about incomplete data. Oversampling is entirely different because it is a kind of feedforward instead of feedback.
In some sense, synchronous conversion is perfect because it does not touch the contents of the data. It only introduces tiny amounts of timing variation, which could be nearly eliminated by using buffers or other stabilization measures.
Here is a pretty good discussion of ASRC at What's Best Forum.
One digital receiver chip which implements ASRC is the Cirrus Logic CS8420. While bit perfect transmission introduces no THD or dynamic range limitation whatever, the CS8420 is specified as having 128dB dynamic range and -117dB THD at 1kHz. That's pretty good, and better than virtually all DAC's, but it is not perfect. Further it seems to me the imperfection is increased by jittery inputs.
Benchmark DACs may have been among the first to include ASRC--they made a big point about it--but I'm suspicious that earlier ones also had this going back to Mark Levinson and possibly even Wadia (though Wadia seems never to have used the term ASRC). High end digital pioneers implemented ASRC in their own FPGA's.
When I asked Kingwa about whether the Master 7 Singularity used synchronous or asynchronous receivers for AES and SPDIF and he replied Asynchronous. However I'm not 100% sure he understood that I was not asking about USB.
In this little discussion, an industry expert says that ASRC is essentially PLL done in the digital domain. That is exactly the idea that has occurred to me in the past month. But once again, I must add that 'the digital domain' means that it alters your audio bits, and such alteration can never be done perfectly, and the imperfections relate to stuff like noise and ground loops in the signal that would otherwise cause only tiny alterations in timing.
On the other hand...Emotiva shows impressive improvement using ASRC. The Emotiva Stealth DC-1 (a inexpensive sigma delta DAC including AES input and balanced outputs which I use for the subs) allows you to turn ASRC on or off. I have generally turned it off, but maybe I shouldn't?
Emotiva has been using the AD1896 ASRC - same a Benchmark DAC 1. (Not sure if that's true of Stealth DC-1 though.)
Amirm at WBF isn't impressed by the Jtest results shown by Emotiva. He says ASRC needs a test to expose its weaknesses the same way Jtest exposes jitter caused by AES/SPDIF.
(I can't believe that Amir and many other posters I've enjoyed reading at WBF are now banned. I made a rambling post to an ages old thread over there a few days ago, so apparently I'm not banned yet. You cannot say that Amir is an objectivist flamethrower, like, say, Ethan Winer--though I liked him also. At one point, I remember a great debate between Amir and Winer but that was at AVS. So I wonder what's up over there. It's not just objectophiles who have been tossed apparently. Other forums were lots of interesting people are now banned include SBAF, over there it seems like over half of all posts are by now banned posters. But SBAF always sounded tricky.)
Update 7/19/17
Here's one of the best discussions I've found about PLL vs ASRC digital input receivers (aka DIR).
It turns out that my new favorite DAC, the Denon DVD-5000, which was considered State of the Art in 1998 (a mere 19 years ago) uses the very well known CS8414 dir by Crystal Semiconductor, which is a standard digital PLL type of receiver (not ASRC. The 8414 was a follow on to the 8412 which many still regard as the best of it's type. The following CS8416 is generally considred not as good. But all of these chips have a self-jitter specification of 200ps (not wonderful). That specification tells us very little, however, about how incoming jitter is suppressed.
Within the ASRC type receivers, there is actual considerable jitter suppression done before the ASRC. The ASRC is said only to encode a tiny portion of the incoming jitter, the "residual" jitter, into the data. Which, as proponents of ASRC say, is precisely what the DAC chips themselves do.
(So, I ask, why don't they leave the DAC chips to do that, as they previously had, and simply use the "superior" jitter suppression to do what it can do without using any explicit ASRC at all? I mean this as a serious question, however I would not be surprised if the ASRC chips handle this residual jitter better than the DAC's do. But where are the numbers? Where are the measurements?)
Generally the ASRC chips have much better self jitter numbers, like 50pS. But the newest synchronous receiver chip, the DIR 9001, also has a self jitter spec of 50pS. This tells us nothing about incoming jitter suppression, and the self jitter specs may have been differently determined, but it is possible that DIR 9001 is better than CS8414. Or not. Some people still seek the old Crystal receivers.
Both ASRC and PLL type receivers require some kind of buffer, or the pre-ASRC jitter rejection could not possibly work. There is some argument at the above link as to how large this buffer needs to be, with some saying it can be quite small. I think I can see why that might be possible in some cases, but I'm not sure if it can accomodate all cases.
USB interfaces are a whole other ball of wax I don't want to think about, along with I2S, as I have detailed in an earlier post, because they inhibit the chaining of digital devices and generally lock you in to proprietary software. That kills the fun, and right now I can't use those interfaces anyway because my style of digital audio relies upon the chaining of digital audio devices, such as the Behringer 2496 DEQ units I use as crossovers and room correction, and the Tact RCS 2.0 I use for volume, balance, and polarity adjustment (though it is capable of much more). USB and I2S assume you are connecting a computer to a DAC, with nothing in between. In principle you could chain USB and I2S devices....but you'd have to write all new operating systems for every step of the chain.
Anyway, SPDIF/AES interfaces can also be implemented in synchronous and asynchronous versions, the asynchronous version generally involving ASRC -- Asynchronous Sample Rate Conversion.
ASRC has always seemed very fishy to me, because it essentially relies upon endless interpolation. The data presented to the ultimate digital converter is not the data you started with.
No interpolation process can be perfect, and especially when in this case it involves guesswork about incomplete data. Oversampling is entirely different because it is a kind of feedforward instead of feedback.
In some sense, synchronous conversion is perfect because it does not touch the contents of the data. It only introduces tiny amounts of timing variation, which could be nearly eliminated by using buffers or other stabilization measures.
Here is a pretty good discussion of ASRC at What's Best Forum.
One digital receiver chip which implements ASRC is the Cirrus Logic CS8420. While bit perfect transmission introduces no THD or dynamic range limitation whatever, the CS8420 is specified as having 128dB dynamic range and -117dB THD at 1kHz. That's pretty good, and better than virtually all DAC's, but it is not perfect. Further it seems to me the imperfection is increased by jittery inputs.
Benchmark DACs may have been among the first to include ASRC--they made a big point about it--but I'm suspicious that earlier ones also had this going back to Mark Levinson and possibly even Wadia (though Wadia seems never to have used the term ASRC). High end digital pioneers implemented ASRC in their own FPGA's.
When I asked Kingwa about whether the Master 7 Singularity used synchronous or asynchronous receivers for AES and SPDIF and he replied Asynchronous. However I'm not 100% sure he understood that I was not asking about USB.
In this little discussion, an industry expert says that ASRC is essentially PLL done in the digital domain. That is exactly the idea that has occurred to me in the past month. But once again, I must add that 'the digital domain' means that it alters your audio bits, and such alteration can never be done perfectly, and the imperfections relate to stuff like noise and ground loops in the signal that would otherwise cause only tiny alterations in timing.
On the other hand...Emotiva shows impressive improvement using ASRC. The Emotiva Stealth DC-1 (a inexpensive sigma delta DAC including AES input and balanced outputs which I use for the subs) allows you to turn ASRC on or off. I have generally turned it off, but maybe I shouldn't?
Emotiva has been using the AD1896 ASRC - same a Benchmark DAC 1. (Not sure if that's true of Stealth DC-1 though.)
Amirm at WBF isn't impressed by the Jtest results shown by Emotiva. He says ASRC needs a test to expose its weaknesses the same way Jtest exposes jitter caused by AES/SPDIF.
(I can't believe that Amir and many other posters I've enjoyed reading at WBF are now banned. I made a rambling post to an ages old thread over there a few days ago, so apparently I'm not banned yet. You cannot say that Amir is an objectivist flamethrower, like, say, Ethan Winer--though I liked him also. At one point, I remember a great debate between Amir and Winer but that was at AVS. So I wonder what's up over there. It's not just objectophiles who have been tossed apparently. Other forums were lots of interesting people are now banned include SBAF, over there it seems like over half of all posts are by now banned posters. But SBAF always sounded tricky.)
Update 7/19/17
Here's one of the best discussions I've found about PLL vs ASRC digital input receivers (aka DIR).
It turns out that my new favorite DAC, the Denon DVD-5000, which was considered State of the Art in 1998 (a mere 19 years ago) uses the very well known CS8414 dir by Crystal Semiconductor, which is a standard digital PLL type of receiver (not ASRC. The 8414 was a follow on to the 8412 which many still regard as the best of it's type. The following CS8416 is generally considred not as good. But all of these chips have a self-jitter specification of 200ps (not wonderful). That specification tells us very little, however, about how incoming jitter is suppressed.
Within the ASRC type receivers, there is actual considerable jitter suppression done before the ASRC. The ASRC is said only to encode a tiny portion of the incoming jitter, the "residual" jitter, into the data. Which, as proponents of ASRC say, is precisely what the DAC chips themselves do.
(So, I ask, why don't they leave the DAC chips to do that, as they previously had, and simply use the "superior" jitter suppression to do what it can do without using any explicit ASRC at all? I mean this as a serious question, however I would not be surprised if the ASRC chips handle this residual jitter better than the DAC's do. But where are the numbers? Where are the measurements?)
Generally the ASRC chips have much better self jitter numbers, like 50pS. But the newest synchronous receiver chip, the DIR 9001, also has a self jitter spec of 50pS. This tells us nothing about incoming jitter suppression, and the self jitter specs may have been differently determined, but it is possible that DIR 9001 is better than CS8414. Or not. Some people still seek the old Crystal receivers.
Both ASRC and PLL type receivers require some kind of buffer, or the pre-ASRC jitter rejection could not possibly work. There is some argument at the above link as to how large this buffer needs to be, with some saying it can be quite small. I think I can see why that might be possible in some cases, but I'm not sure if it can accomodate all cases.
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